Phase combiner circuits are used for frequency multiplication, in particular for generating output clock signals having a higher frequency than an input clock signal. In such phase combiner circuits, conventionally a plurality of signals having a same frequency, but different phases are generated, for example using a delay locked loop (DLL) delaying an input signal or using a ring oscillator. This plurality of signals having different phases is then combined to form an output signal having a higher frequency.
Conventional ways for combining the plurality of signals having different phases include dynamically switching multiplexers, where one of the plurality of signals is for-warded to an output of the multiplexer in each clock cycle, for example controlled by a counter. This requires a fast switching of the multiplexer in each clock cycle. Another conventional approach uses a static chain of logic gates, for example exclusive OR (XOR) gates. Such approaches are usually prone to duty cycle distortions of the input signal and could even potentially lead to glitches on an output signal, for example, if a duty cycle is degrading over a delay line used for generating the input signals having the plurality of phases. For duty cycle correction or adjustment, additional circuits have to be used like current starved buffers or inverters, which require a control of transistor currents for duty cycle adjustment.